1. Field of the Invention
This disclosure relates to computer processor operation, and more particularly to handling of exceptions such as an interrupt request during a period in which the processor is waiting for completion of a memory access.
2. Description of the Related Art
Microprocessors determine the speed and power of personal computers, and a growing number of other computational devices (such as appliances, telephones or personal digital assistants) by handling most of the data processing in the device. Microprocessors typically include at least three functional groups: the external interface unit, the control unit, and the arithmetic logic unit (ALU). The control and the ALU units combine to form the central processing unit (CPU). The microprocessor also includes memory to store program instructions to be executed. The CPU fetches instructions from the memory and proceeds to decode and execute them. Within the CPU, the ALU handles the mathematical computations and logical operations that are performed by the microprocessor, and the control unit controls the operation of the microprocessor by fetching instructions from the external interface unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step within the instruction is being executed.
Most modern microprocessors employ various design methods to improve the processing speed for executing a set of instructions. These include pipelining, speculative and out-of-order execution, and multiple instruction fetch. Pipelining is a key design technique employed to improve processing speed and employs multiple instructions overlapped in execution. Thus, pipelining increases the CPU instruction throughput but it does not reduce the execution time of an individual instruction. Practically all microprocessors today employ some level of pipelining to improve processing speed. A pipeline consists of sequential stages, wherein each stage completes a part of an execution of an instruction passing through the pipeline. Thus, different stages in the pipeline are completing parts of different instructions in parallel. Each of these stages is commonly referred to as a pipe stage. These pipe stages are connected sequentially to form a pipe, where instructions enter at one end., proceed through the pipe stages, and exit at the other end.
There are many factors influencing a microprocessor system""s operational speed. One of these factors is exception handling. Exceptions arise in a microprocessor system whenever there is a need for the normal flow of program execution to be broken. For example, this flow may be broken so that the microprocessor can be diverted to handle an interrupt from an external I/O device. An interrupt causes a microprocessor to suspend execution of the current task being performed by the CPU in order to execute a specific software routine, known as an interrupt service routine (ISR). This routine comprises a set of software instructions typically unrelated to the instructions being executed by the microprocessor at the time the interrupt is signaled. An interrupt request is often initiated, for example, by an external I/O device to signal that the I/O device is ready for a data transfer.
In a typical interrupt sequence, the I/O device, or xe2x80x9cperipheralxe2x80x9d, first sends an interrupt request signal to the microprocessor requesting a data transfer service. In the case of a pipelined processor, a xe2x80x9cbreakpointxe2x80x9d is typically established in the pipeline, at which point the sequence of instructions in the pipeline can be interrupted relatively conveniently. Instructions scheduled for execution after this breakpoint are discarded from the pipeline, and instructions scheduled for execution before this breakpoint are allowed to complete during subsequent execution of the pipeline. In the case of a non-pipelined microprocessor, the microprocessor typically finishes the instruction currently being processed prior to handling the interrupt request. Either before execution of or as a part of the ISR, the contents of critical registers may be stored into pre-assigned memory locations for use in resumption of the main program subsequent to servicing the interrupt request. The processor also stores the contents of the program counter prior to the ISR. The program counter allows the processor to track which location in program memory the processor may go to fetch the instruction and typically contains the address of the next instruction to be fetched. After the above-described preparatory actions are done, the microprocessor proceeds to execute the ISR. Service of the interrupt may therefore include these preparatory actions such as discarding instructions from the pipeline as well as execution of the ISR. After completion of the ISR (or sometimes as part of the routine), data from the stored critical registers and program counter are reloaded back into their respective memory locations such that the microprocessor is then restored back to its xe2x80x9cpre-interruptxe2x80x9d status and proceeds to resume execution of the main program.
The time (typically measured in clock cycles) between when the initial interrupt request occurs and the execution of the ISR is started may be defined as the overall latency associated with handling an interrupt. This overall latency includes any latency associated with establishing a breakpoint and clearing pipeline instructions (described herein as xe2x80x9cinterrupt pipeline latencyxe2x80x9d). Another component of the overall latency may include, for example, any latency associated with disabling service of the interrupt for a period of time to allow execution of critical instructions to complete unperturbed.
In addition to the latency components described above, additional contributions to the overall latency can be incurred in situations for which the processor is waiting for completion of an instruction that was executing when the interrupt was received. For example, in an instruction calling for a memory access, the memory access may not be able to be completed in the current clock cycle, and the microprocessor is forced to simply wait until the memory access can be completed in a subsequent clock cycle. In other words, the microprocessor may not be able to perform other tasks or execute further instructions due to this delay in the memory access. This latency, defined herein as interrupt memory delay latency, measures the time it takes for the microprocessor to perform the memory access before beginning interrupt service. Depending on memory configurations used in the microprocessor system, this latency can be quite long. Such latency can be present, for example, in multi-microprocessor systems in which the microprocessors interface with a pooled memory system, or in a microprocessor system for which some memories have slow access times compared to the speed of the microprocessor.
Ideally, the overall interrupt latency should be as low as possible to increase overall microprocessor system performance. Long overall interrupt latencies of I/O devices can detrimentally affect the overall speed of the program being executed, particularly when the program calls for real-time data transfer between I/O devices and the microprocessor. For example, in a streaming video application which requires a minimum data transfer rate to sustain the amount of data required to provide smooth and seamless motion-video, long interrupt latencies between the microprocessor and the video graphics system can cause many frames of the video to be dropped during playback.
It would therefore be desirable to provide a method and system for handling exceptions such as an interrupt request with low overall latency to improve microprocessor system performance.
The issues described above are in large part addressed by a method and processor for handling an exception received by the processor, where service of the exception is initiated while waiting for completion of a memory access attempt by the processor. In an embodiment, the processor employs a xe2x80x9cretryxe2x80x9d signal in a determination of whether to initiate service of an exception received in response to the exception. The retry signal is associated with a memory access attempt by the microprocessor. In particular, the retry signal may be asserted when a memory access is delayed. The retry signal in this case corresponds to a suspension of the instruction execution by the processor until the memory access is completed and the retry signal de-asserted. In one embodiment, the exception may be an interrupt. Advantageously then, employing the retry signal may result in lower overall interrupt latency for interrupts occurring during a period of delayed memory access. During a period of delayed memory access, the processor typically is forced to wait until the memory access is available upon which execution of instructions may then resume. If an interrupt request occurs during this period, service of the interrupt request would also be delayed until at least after the memory access becomes available. In contrast, this interrupt memory delay latency may be reduced and possibly completely avoided by employing the retry signal such that an interrupt request may be serviced during this period of delayed memory access. This would result in a reduction in overall interrupt latency. In addition, it may also result in increasing processor bandwidth performance (i.e., number of instructions per second), due to the fact that the processor is no longer idling during the delayed memory access, but instead performing operations on an interrupt request.
In an embodiment of a method described herein for handling an exception, the status (asserted or non-asserted) of the retry signal is employed in a determination of whether to initiate service of the: exception received in response to the exception. In an embodiment for which the exception is an interrupt signal, the interrupt service may be initiated if the retry signal is asserted, regardless of a degree of completion of an instruction by the processor. This is in contrast to waiting until completion of the current instruction before starting interrupt service, as is typically done. In one embodiment, the initiation of the interrupt service is performed within a predetermined time interval after receiving an asserted interrupt and may be performed in response to the subsequent clock signal following receiving the asserted interrupt during an asserted retry signal. The method may further comprise completing the interrupt service and subsequently resuming instruction execution by the processor, where the instruction execution is resumed beginning with a last instruction attempted before the suspension of the instruction execution by the processor. This last instruction attempted is typically the memory access attempted by the processor Which resulted in the asserted retry signal and the suspension of instruction execution.
A processor suitable for use with a method such as that described above is also described herein. In one embodiment, the processor includes interrupt handling logic adapted to produce an interrupt service initiation signal which, when asserted, enables initiation of interrupt service in response to an interrupt request signal. The interrupt service initiation signal is produced as a function of the interrupt request signal and the retry signal described above. In an embodiment, the interrupt service initiation signal is asserted when both the interrupt request signal and the retry signal are asserted. The interrupt handling logic, in one embodiment, includes a first circuit adapted to generate an asserted first output signal when either the retry signal or an instruction completion signal are asserted, in which the instruction completion signal is associated with completion of a last portion of an instruction execution. The interrupt handling logic may further include a second circuit adapted to generate an asserted second output signal when both the interrupt request signal and the first output signal are asserted. The interrupt service initiation signal may be produced upon an output terminal, and a latching circuit may be employed to transfer the second output signal to the output terminal to produce the interrupt service initiation signal.
In another embodiment of a processor suitable for use with the method described herein, the processor includes address selection logic adapted to select an instruction address as a function of the retry signal and an interrupt service initiation signal as described above. The address selection logic, in one embodiment, includes a first circuit adapted to generate an asserted first output signal when both the retry signal and the interrupt service initiation signal are asserted. The address selection logic may further include a second circuit adapted to select the instruction address as a function of the first output signal. In an embodiment for which the retry signal is asserted, for example, the second circuit may select an instruction address of the memory access which was delayed and caused the retry signal to be asserted. In an embodiment, the second circuit may include a selection circuit having its output connected to one of two inputs. The processor may further include interrupt handling logic as described above, to produce the interrupt service initiation signal as a function of the interrupt request signal and the retry signal.